`include "MAC_define.v"
`include "protocol_define.v"
`include "work_mode_define.v"
`define SRAM_2P_UHDE_SVT_MVT_ARM_DISABLE_DUMMY_CYCLE
module NP_1G_UDP_system (
    //----------------------------------------------
    // clock input
    //----------------------------------------------
    input               clk_100M                    ,
    input               clk_125M                    ,
    input               clk_125M_90phase            ,
    input               dcm_locked                  ,
    input               AHB_clk_125M                ,
    //----------------------------------------------
    // reset input
    //----------------------------------------------
    input               reset                       ,
    input   [11:0]      ram_dp_cfg_register         ,
    input   [9:0]       ram_2p_cfg_register         ,
    //----------------------------------------------
    // AHB interface
    //----------------------------------------------
    output  [31:0]      AHB_haddr_m                 ,
    output  [31:0]      AHB_hwdata_m                ,
    output              AHB_hwrite_m                ,
    output  [2:0]       AHB_hsize_m                 ,
    output  [2:0]       AHB_hburst_m                ,
    output  [1:0]       AHB_htrans_m                ,
    output  [3:0]       AHB_hmaster_m               ,
    output              AHB_hnonsec_m               ,
    output              AHB_hexcl_m                 ,
    output              AHB_hmasterlock_m           ,
    output  [6:0]       AHB_hprot_m                 ,
    input   [31:0]      AHB_hrdata_m                ,
    input               AHB_hready_m                ,
    input               AHB_hresp_m                 ,

    //----------------------------------------------
    // PHY interface
    //----------------------------------------------
    // reset "PHY"
    output              phyrst_n                    , 
    // RGMII receive channel
    input               rgmii_rx_clk                ,
    input               rgmii_rx_ctrl               ,
    input   [3:0]       rgmii_rxd                   ,
    // RGMII send channel
    output              rgmii_tx_clk                ,
    output              rgmii_tx_ctrl               ,
    output  [3:0]       rgmii_txd                   
) ;

    //----------------------------------------------
    // MAC wire declare
    //----------------------------------------------
    // rx channel
    wire            mac_rx_rdy ;
    wire [31:0]     mac_rx_data ;
    wire [1:0]      mac_rx_mod ;
    wire            mac_rx_sav ;
    wire            mac_rx_val ;
    wire            mac_rx_sop ;
    wire            mac_rx_eop ;
    wire [5:0]      mac_rx_err ;
    wire [10:0]     mac_rx_data_length ;
    // tx channel
    wire            mac_tx_rdy ;
    wire [31:0]     mac_tx_data ;
    wire [1:0]      mac_tx_mod ;
    wire            mac_tx_sav ;
    wire            mac_tx_val ;
    wire            mac_tx_sop ;
    wire            mac_tx_eop ;
    // ----------------------------------------------
    // MAC instance
    // ----------------------------------------------
    MAC_top_top inst_MAC(
        .Reset              (reset              ),
        .phyrst_n           (phyrst_n           ),
        //clock block       
        .Clk_user           (clk_100M           ),
        .Clk_125M           (clk_125M           ),
        .Clk90              (clk_125M_90phase   ),
        .ram_dp_cfg_register(ram_dp_cfg_register),
        .dcm_locked         (dcm_locked         ),
        //RGMII interface
        .rgmii_rx_clk       (rgmii_rx_clk       ),
        .rgmii_rxd          (rgmii_rxd          ),
        .rgmii_rx_ctl       (rgmii_rx_ctrl      ),
        .rgmii_tx_clk       (rgmii_tx_clk       ),
        .rgmii_txd          (rgmii_txd          ),
        .rgmii_tx_ctl       (rgmii_tx_ctrl      ),
        
        // rx channel
        .ff_rx_rdy          (mac_rx_rdy         ), // input
        .ff_rx_data         (mac_rx_data        ),
        .ff_rx_mod          (mac_rx_mod         ),
        .ff_rx_dsav         (mac_rx_sav         ),
        .ff_rx_dval         (mac_rx_val         ),
        .ff_rx_sop          (mac_rx_sop         ),
        .ff_rx_eop          (mac_rx_eop         ),
        .rx_err             (mac_rx_err         ), // no use
        .frame_length       (mac_rx_data_length ),
        // tx channel
        .ff_tx_rdy          (mac_tx_rdy         ),
        .ff_tx_data         (mac_tx_data        ), // input
        .ff_tx_mod          (mac_tx_mod         ), // input
        .ff_tx_wren         (mac_tx_val         ), // input
        .ff_tx_sop          (mac_tx_sop         ), // input
        .ff_tx_eop          (mac_tx_eop         ), // input
        .ff_tx_err          (1'b0               ), // input
        .ff_tx_septy        (                   ),
        // FIFO data counter 
        .Fifo_data_count    (                   )
    ) ;

    Eth_1G_UDP_system inst_Eth_1G_UDP_system(
        .clk_in                      (clk_100M          ), // UDP system clock
        .reset                       (reset             ), // reset pin
        .ram_dp_cfg_register         (ram_dp_cfg_register),
        .ram_2p_cfg_register         (ram_2p_cfg_register),
        
        //----------------------------------------------
        // MAC interface
        //----------------------------------------------
        .mac_rx_rdy                  (mac_rx_rdy        ) ,
        .mac_rx_data                 (mac_rx_data       ) ,
        .mac_rx_mod                  (mac_rx_mod        ) ,
        .mac_rx_sav                  (mac_rx_sav        ) ,
        .mac_rx_val                  (mac_rx_val        ) ,
        .mac_rx_sop                  (mac_rx_sop        ) ,
        .mac_rx_eop                  (mac_rx_eop        ) ,
        .mac_rx_data_length          (mac_rx_data_length) ,

        .mac_tx_rdy                  (mac_tx_rdy        ) ,
        .mac_tx_data                 (mac_tx_data       ) ,
        .mac_tx_mod                  (mac_tx_mod        ) ,
        .mac_tx_val                  (mac_tx_val        ) ,
        .mac_tx_sop                  (mac_tx_sop        ) ,
        .mac_tx_eop                  (mac_tx_eop        ) ,

        //----------------------------------------------
        // AHB interface
        //----------------------------------------------
        .NP_clk_312M                (AHB_clk_125M       ) , 
        .AHB_haddr_m                (AHB_haddr_m        ) ,
        .AHB_hwdata_m               (AHB_hwdata_m       ) ,
        .AHB_hwrite_m               (AHB_hwrite_m       ) ,
        .AHB_hsize_m                (AHB_hsize_m        ) ,
        .AHB_hburst_m               (AHB_hburst_m       ) ,
        .AHB_htrans_m               (AHB_htrans_m       ) ,
        .AHB_hmaster_m              (AHB_hmaster_m      ) ,
        .AHB_hnonsec_m              (AHB_hnonsec_m      ) ,
        .AHB_hexcl_m                (AHB_hexcl_m        ) ,
        .AHB_hmasterlock_m          (AHB_hmasterlock_m  ) ,
        .AHB_hprot_m                (AHB_hprot_m        ) ,
        .AHB_hrdata_m               (AHB_hrdata_m       ) ,
        .AHB_hready_m               (AHB_hready_m       ) ,
        .AHB_hresp_m                (AHB_hresp_m        )
    ) ;

endmodule
